Marina Bellido Rodriguez

Georgia Tech M.S. Student | Electrical & Computer Engineering

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About

I am a first-year M.S. student in Electrical and Computer Engineering at Georgia Tech. I graduated from Harvey Mudd College in May 2026 with a B.S. in General Engineering and an ECE specialization. As a Clay-Wolkin Fellow in Harvey Mudd’s VLSI Lab, I helped develop an open-source RISC-V architectural verification suite that became RISC-V International’s official v4.0 Unprivileged Certification Test Suite, recognized by the 2026 TCMM Open Source Hardware Contribution Award. My work spans computer architecture, hardware verification, and analog design. I am always excited to learn, build, and connect with other engineers.

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Education & Skills

Georgia Institute of Technology, Atlanta, GA
M.S. Electrical and Computer Engineering, Expected May 2028

Harvey Mudd College, Claremont, CA
B.S. General Engineering, ECE specialization, May 2026
GPA: 3.73/4.00; Minor: Environmental Analysis
Tau Beta Pi Engineering Honor Society

Analog: Xschem, Magic, LTspice, Synopsys, COMSOL, MATLAB
Programming: SystemVerilog, C, RISC-V Assembly, C++, Python, Java, Modelica
Verification: Questa Intel, Quartus Prime, ImperasDV, RISCOF, SAIL, Spike, GCC, Git
Hardware: CORE-V Wally, STM32, iCE40 FPGA, Arduino, Teensy, SiFive FE310, DE0-CV
Fabrication: 3D printing, laser cutting, welding, waterjet, lathe, mill, SolidWorks
Languages: English (C1), German (B2), Spanish and Catalan (native)

Work Experience

Breker Verification Systems, Inc. | Systems Integration Engineer (Team Lead)

Aug 2025 – May 2026 | Claremont, CA

  • Led three subteams and served as the primary industry liaison, coordinating weekly planning, schedules, final deliverables, and project reports.
  • Authored PMP and Debug (Sdext) test plans; built a socket-based JTAG sniffer for lightweight OpenOCD–Spike debug integration with Breker’s graph-based framework.
10xEngineers RISC-V verification work

10xEngineers | RISC-V Architectural Functional Verification Engineer

Jan 2025 – May 2025 | Claremont, CA

  • Developed RISC-V Architectural Verification Test Suite components, including privilege tests and functional-coverage updates for unprivileged tests.
  • Designed assembly-level endianness tests; contributed 12,600+ additions to openhwgroup/cvw-arch-verif, merged upstream.
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Sokil Imaging UAV magnetometry system

Sokil Imaging | UAV Systems Integration Engineer

Jun 2024 – Aug 2025 | Claremont, CA

  • Co-designed and fabricated a second-generation UAV magnetometry system for humanitarian demining; integrated it with the drone platform.
  • Configured ExpressLRS control and telemetry using CRSF and MAVLink.
Sokil on LinkedIn
Endura Technologies

Endura Technologies | Software Engineering Intern

May 2023 – Jun 2023 | San Diego, CA

  • Created a Python GUI to accelerate PMIC evaluation.

Projects

Microprocessor Systems Lab Portfolio

E155 Coursework

Browse the full collection of FPGA, microcontroller, and embedded-systems labs.

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Invisible Drum Set — FPGA/MCU Audio System

Dec 2025

Built an STM32/iCE40 gesture instrument with two BNO055 IMUs, 400 kHz I²C, SPI sound-ID transfer, WAV decoding, and 12-bit DAC playback.

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Multicycle RISC-V processor datapath

Multicycle RISC-V Processor

Nov 2024

Designed and verified a multicycle RISC-V processor in SystemVerilog with unified memory and custom control logic; passed the Intel Quartus test suite.

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CMOS Operational Amplifier Design & Layout

Oct 2026

Designed and laid out a compensated two-stage GF180 CMOS op-amp; verified post-layout feedback, transient, and noise performance and passed DRC/LVS.

Discrete BJT Op-Amp Design & Stability

Apr 2026

Designed, built, and characterized a five-stage discrete BJT op-amp; validated open- and closed-loop behavior against analysis and simulation.

RF receiver project

RF Receiver Design for Communication Systems

Dec 2024

Built a direct-downconversion/direct-sampling receiver with Mini-Circuits modules and compared theoretical and measured signal, noise, and distortion.

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Low-Power Half-Precision FMA for Graphics

May 2025

Designed an IEEE 754 half-precision FMA in Verilog for graphics; passed Verilator lint and baseline functional tests.

Autonomous underwater vehicle

Autonomous Underwater Vehicle — Hardware Lead

Jan 2024 – May 2024

Led hardware development of an autonomous underwater vehicle with Teensy 4.1 sensor integration and proportional autonomous navigation.

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Van's RV-12 aircraft build

Van’s RV-12 Light-Sport Aircraft Build

2024 – 2025

Constructed a two-seat Van’s RV-12 with a 100 hp Rotax engine and Garmin VFR avionics.

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Fellowship & Research

Clay-Wolkin Fellowship research

Clay Wolkin HMC Research Fellowship / RISC-V International-Sponsored Research

Nov 2024 – Feb 2026

  • Developed RISC-V International’s official v4.0 Unprivileged Certification Test Suite, supporting certification infrastructure recognized by the 2026 TCMM Open Source Hardware Contribution Award.
  • Contributed to CORE-V Wally rv64gc and rv32gc extensions, advancing configurations toward Technology Readiness Level 5.
  • Authored Supervisor ISA normative rules and linked them to test plans; reviewed RISC-V System-on-Chip Design, acknowledged in publication.
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RESIST Lab heat-pump research

Reducing Costs for Space- and Water-Heating in Multifamily Buildings

May 2024 – Jul 2024

  • Modeled and validated a field-demonstrated system in Modelica using live data, then extended the validated model to additional cases using model-based design.
  • Explored heat-pump integration with phase-change thermal storage to improve energy efficiency and flexibility during electrification.
  • Contributed to a research paper under review with the U.S. Department of Energy.
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Publications & Acknowledgments

RISC-V System-on-Chip Design

  • Acknowledged for reviewing the book by David Harris.

Contact

Location: Atlanta, GA
Email: marina.bellido25@gmail.com
Phone: +1 840-999-0466
LinkedIn: linkedin.com/in/marina-bellido-hmc
GitHub: github.com/Marina-Bellido

Marina Bellido Rodriguez